Processing node including a plurality of processor cores and an interconnect configurable in a test-mode to cause first and second transaction source indicators to be interchanged

ABSTRACT

In one embodiment, a processing node includes a plurality of processor cores and a reconfigurable interconnect. The processing node also includes a controller configured to schedule transactions received from each processor core. The interconnect may be coupled to convey between a first processor core and the controller, transactions that each include a first corresponding indicator that indicates the source of the transaction. The interconnect may also be coupled to convey transactions between a second processor core and the controller, transactions that each include a second corresponding indicator that indicates the source of the transaction. When operating in a first mode, the interconnect is configurable to cause the first indicator to indicate that the corresponding transactions were conveyed from the second processor core and to cause the second indicator to indicate that the corresponding transactions were conveyed from the first processor core.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention is related to the field of chip multiprocessors (CMP)and, more particularly, to reconfiguration of resources within a CMP.

2. Description of the Related Art

Chip multiprocessors (CMPs) are becoming increasingly popular. A CMP hastwo or more processor cores implemented on the same integrated circuit(IC) device. The increase in popularity may be due, at least in part, tothe notion that a CMP may be a more efficient use of the millions oftransistors that may be included on an integrated circuit than, forexample, a more elaborate single processor.

The testing of processors involves the generation and execution of testfiles that include a large number of test vectors. Due to their size,the test vectors may require long execution times and a great deal ofstorage. Test vector memory is one of the cost considerations whenbuying test equipment. When the processor is a CMP, there may bemultiple processor cores in one IC. To test a CMP with two cores, forexample, due to the interconnection of the two cores, a set of testvectors may be used to test one core and a second set of test vectorsmay be used to test the second core. In addition, a third set of testvectors may be used to test the inter-functionality of the two cores.This arrangement may strain available test vector memory and testgeneration time.

SUMMARY

Various embodiments of a processing node including a plurality ofprocessor cores and a reconfigurable interconnect are disclosed. In oneembodiment, each processor core may be configured to execute programinstructions. The processing node also includes a controller configuredto schedule transactions received from each processor core. Theinterconnect may be coupled to convey between a first processor core andthe controller, transactions that each include a first correspondingindicator that indicates the source of the transaction. The interconnectmay also be coupled to convey transactions between a second processorcore and the controller, transactions that each include a secondcorresponding indicator that indicates the source of the transaction.When operating in a first mode, the interconnect is configurable tocause the first indicator to indicate that the correspondingtransactions were conveyed from the second processor core and to causethe second indicator to indicate that the corresponding transactionswere conveyed from the first processor core.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of one embodiment of a computer system.

FIG. 2 is a block diagram of one embodiment of the interconnect of FIG.1.

FIG. 3 is a block diagram of another embodiment of a computer system.

While the invention is susceptible to various modifications andalternative forms, specific embodiments thereof are shown by way ofexample in the drawings and will herein be described in detail. Itshould be understood, however, that the drawings and detaileddescription thereto are not intended to limit the invention to theparticular form disclosed, but on the contrary, the intention is tocover all modifications, equivalents, and alternatives falling withinthe spirit and scope of the present invention as defined by the appendedclaims. Note, the headings are for organizational purposes only and arenot meant to be used to limit or interpret the description or claims.Furthermore, note that the word “may” is used throughout thisapplication in a permissive sense (i.e., having the potential to, beingable to), not a mandatory sense (i.e., must). The term “include” andderivations thereof mean “including, but not limited to.” The term“connected” means “directly or indirectly connected,” and the term“coupled” means “directly or indirectly coupled.”

DETAILED DESCRIPTION

Turning now to FIG. 1, a block diagram of one embodiment of a computersystem 10 is shown. In the illustrated embodiment, the computer system10 includes a processing node 12 coupled to memory 14 and to peripheraldevices 13A–13B. The node 12 includes processor cores 15A–15B that arecoupled to a interconnect 50 via connection 51 and connection 52,respectively. Interconnect 50 is in turn coupled to a node controller 20via connection 53. The node controller 20 is further coupled to a memorycontroller 22 and a plurality of HyperTransport™ (HT) interface circuits24A–24C. The HT circuit 24C is coupled to the peripheral device 13A,which is coupled to the peripheral device 13B in a daisy-chainconfiguration (using HT interfaces, in this embodiment). The remainingHT circuits 24A–B may be connected to other similar processing nodes(not shown) via other HT interfaces on those nodes (not shown). Thememory controller 22 is coupled to the memory 14. In one embodiment,node 12 may be a single integrated circuit chip comprising the circuitryshown therein in FIG. 1. That is, node 12 may be representative of achip multiprocessor (CMP). Other embodiments may implement the node 12as two or more separate integrated circuits, as desired within a singlepackage. Any level of integration or discrete components may be used.

In one embodiment, node controller 20 may generally be configured toroute communications between the processor cores 15A–15B, the memorycontroller 22, and the HT circuits 24A–24C dependent upon thecommunication type, the address in the communication, etc. In oneembodiment, the node controller 20 may include a system request queue(SRQ) (not shown) into which received communications are written by thenode controller 20. The node controller 20 may schedule communicationsfrom the SRQ for routing to the destination or destinations among theprocessor cores 15A–15B, the HT circuits 24A–24C, and the memorycontroller 22. In one embodiment, node controller 20 may employ acrossbar-type switching circuit (not shown) to route the communicationsto the various destinations.

Generally, the processor cores 15A–15B may use interconnect 50 tointerface to the node controller 20 to communicate with other componentsof the computer system 10 (e.g. peripheral devices 13A–13B, otherprocessor cores (not shown in FIG. 1), the memory controller 22, etc.).The interconnect 50 may be designed in any desired fashion.Cache-coherent communication may be defined for the interconnect 50, insome embodiments. In one embodiment, communication on the interfacesbetween the node controller 20 and the processor cores 15A–15B may be inthe form of packets similar to those used on the HT interfaces. In otherembodiments, any desired communication or transaction may be used (e.g.transactions on a bus interface, packets of a different form, etc.). Inother embodiments, the processor cores 15A–15B may share an interface tothe node controller 20 (e.g. a shared-bus interface). Generally, thecommunications from the processor cores 15A–15B may include requestssuch as read operations (to read a memory location or a registerexternal to the processor core) and write operations (to write a memorylocation or external register), responses to probes (for cache-coherentembodiments), interrupt acknowledgements, and system managementmessages, etc.

As described in greater detail below, interconnect 50 may be aconfigurable interconnect between each of the processor cores 15A–15Band the node controller 20. More particularly, in one embodiment,interconnect 50 may operate in various modes. When operating in a firstmode such as a test mode, for example, interconnect 50 may be configuredvia a configuration input port 55 to interchange the connections betweeneach of processor core 15A and processor core 15B and node controller 20such that transactions originating at one processor core (e.g., 15A) aremade to look as if they originated at the other processor core (e.g.,15B). In one embodiment, interconnect 50 may be configurable tologically swap processor 15A and 15B. Doing so may facilitate using oneset of test vectors to test both of the processor cores 15, one at atime. Furthermore, during execution of certain dual-core tests,interconnect 50 may be configurable to change an arbitration priority ofthe processor cores in the event that a request from each processor corearrives at interconnect 50 simultaneously. In another mode, theinterconnect 50 may be configured to allow normal communications betweenprocessors 15 and node controller 20.

In one embodiment, the configuration input port 55 may be a test portsuch as, for example, a serial boundary-scan port that is also referredto as a Joint Test Action Group (JTAG) boundary scan port. A JTAG portis a five-pin port having signals designated TRST, TCK, TMS, TDI, andTDO. Additional details regarding this type of port may be found in theIEEE 1149 standard. As such, a value may be scanned into configurationinput port 55 and stored within interconnect 50.

The memory 14 may include any suitable memory devices. For example, amemory 14 may comprise one or more RAMBUS DRAMs (RDRAMs), synchronousDRAMs (SDRAMs), double data rate (DDR) SDRAM, static RAM, etc. Thememory controller 22 may comprise control circuitry for interfacing andcontrolling access to the memories 14. Additionally, the memorycontroller 22 may include request queues for queuing memory requests,etc.

The HT circuits 24A–24C may comprise a variety of buffers and controlcircuitry for receiving packets from an HT link and for transmittingpackets upon an HT link. The HT interface comprises unidirectional linksfor transmitting packets. Each HT circuit 24A–24C may be coupled to twosuch links (one for transmitting and one for receiving). A given HTinterface 24 may be operated in a cache-coherent fashion (e.g. betweenprocessing nodes) or in a non-coherent fashion (e.g. to/from peripheraldevices 13A–13B). In the illustrated embodiment, the HT circuits 24A–24Bare not in use, and the HT circuit 24C is coupled via non-coherent linksto the peripheral devices 13A–13B.

The peripheral devices 13A–13B may be any type of peripheral devices.For example, the peripheral devices 13A–13B may include devices forcommunicating with another computer system to which the devices may becoupled (e.g. network-interface cards, circuitry similar to anetwork-interface card that is integrated onto a main circuit board of acomputer system, or modems). Furthermore, the peripheral devices 13A–13Bmay include video accelerators, audio cards, hard- or floppy-disk drivesor drive controllers, Small Computer Systems Interface (SCSI) adaptersand telephony cards, sound cards, and a variety of data acquisitioncards such as General Purpose Interface Bus (GPIB) or field businterface cards. It is noted that the term “peripheral device” isintended to encompass input/output (I/O) devices.

Generally, a processor core 15A–15B may include circuitry that isdesigned to execute instructions defined in a given instruction setarchitecture. That is, the processor core circuitry may be configured tofetch, decode, execute, and store results of the instructions defined inthe instruction set architecture. For example, in one embodiment,processor cores 15A–15B may implement the ×86 architecture. Theprocessor cores 15A–15B may comprise any desired configurations,including super-pipelined, superscalar, or combinations thereof. Otherconfigurations may include scalar, pipelined, non-pipelined, etc.Various embodiments may employ out-of-order, speculative execution orin-order execution. The processor core may include microcoding for oneor more instructions or other functions, in combination with any of theabove constructions. Various embodiments may implement a variety ofother design features such as caches, translation look-aside buffers(TLBs), etc.

It is noted that, while the present embodiment uses the HT interface forcommunication between nodes and between a node and peripheral devices,other embodiments may use any desired interface or interfaces for eithercommunication. For example, other packet-based interfaces may be used,bus interfaces may be used, various standard peripheral interfaces maybe used (e.g., Peripheral Component Interconnect (PCI), PCI Express™,etc.), etc.

Referring to FIG. 2, a block diagram of one embodiment of interconnect50 is shown. Interconnect 50 includes a control unit 251 coupled to twoprocessor request buffers 210 and 220. Control unit 251 is also coupledto a response buffer 275. Interconnect 50 further includes an arbiter280 coupled to control a request multiplexer 285. The request buffer 210is coupled to receive transactions from processor core 15A viaconnection 51 and request buffer 220 is coupled to receive transactionsfrom processor core 15B via connection 52. In addition, multiplexer 285and response buffer 275 are coupled to node controller 20 of FIG. 1 viaconnection 53.

In the illustrated embodiment, transactions received from processor core15A–15B may include information such as address, data, control, and avalid bit. Accordingly, buffers 210 and 220 include fields correspondingto those types of information. In addition, buffers 210 and 220 eachinclude a source field, designated src 211 and src 221, respectively.The source field includes an indicator that indicates the source of thetransaction. In one embodiment, the src field may include one or morebits that may be encoded. For example, to identify processor 15A as thesource of a transaction, the src field may be encoded with a 00 and toidentify processor 15B as the source of a transaction, the src field maybe encoded with a 01. In one embodiment, the source information is notpart of the transaction sent from either processor core, but is insteadadded to the transaction once the transaction is received in buffer 210and 220. However, in other embodiments, the source information may bepart of the transaction sent from the processor cores, but as describedfurther below, may be modified.

In the illustrated embodiment, control unit 251 includes a storage 253and a valid bit control unit designated V control 256. Storage 253 maybe any type of storage such as a register, for example, that may store aconfiguration value. The configuration value may be stored withinstorage 253 at start-up or dynamically during operation. In oneembodiment, the configuration value stored within storage 253 maydetermine what values are stored within the src fields 211 and 221. Forexample, in one embodiment, upon power-up and reset, a value of zero maybe stored in storage 253. This zero value may cause interconnect 50 tooperate in a normal mode. In this normal mode, control unit 251 maystore a value in src field 211 indicating that processor core 15A is thesource of transactions received in buffer 210. In addition, control unit251 may also store a value in src field 221 indicating that processorcore 15B is the source of transactions received in buffer 220.

However, during operation, a different configuration value (e.g., logicvalue of one) may be stored within storage 253. This different value maycause interconnect 50 to operate in a test mode. In the test mode,control unit 251 may store a value in src field 211 indicating thatprocessor core 15B is the source of transactions received in buffer 210.In addition, control unit 251 may also store a value in src field 221indicating that processor core 15A is the source of transactionsreceived in buffer 220. It is noted that in one embodiment, storage 253may be accessed during operation via configuration input port 55, whichmay be a JTAG port as described above. By swapping the src indicators,the processor cores and their respective connections have beeneffectively logically swapped. As described above, swapping theprocessor core connections may facilitate using one set of test vectorsto test both of the processor cores 15.

Further, in one embodiment swapping the processor core connections mayalso allow a different core to be used as a boot-strap processor (BSP)in the event that the first processor core is non-functional. In such anembodiment, the src fields may be changed to indicate that a differentcore is the BSP; thereby allowing the processing node 12 to boot up andfunction with at least one processor core.

In the illustrated embodiment, transactions received into buffer 275from node controller 20 may include information such as address, data,control, destination and a valid bit. Thus, buffer 275 may includefields corresponding to that information. The destination value may be avalue that corresponds to processor core 15A or processor core 15B. Inone embodiment, the destination value may be similar to the src values(e.g., a 00 or 01, respectively).

In one embodiment, the response transactions sent from node controller20 may be presented to both of processor cores 15A–15B. However, onlyone of the processor cores (e.g., the processor core that was the sourceof the corresponding request transaction) will see a valid bit thatindicates a valid transaction. The valid bit presented to the processorcores may not be the valid bit that was sent from node controller 20.For example, V control 256 may generate a new valid bit for each of theprocessor cores 15A–15B. In one embodiment, V control 256 may comparethe destination value of the response transaction in buffer 275 to thesrc value in 211 and 221 to determine to which processor core theresponse should go. V control 256 may generate a valid bit thatindicates a valid transaction for the processor core associated with thesrc value that matches the destination value. Thus, only the processorcore that sees a transaction and a valid bit that indicates a validtransaction may latch the response transaction.

It is noted that, while the computer system 10 illustrated in FIG. 1includes one processing node 12, other embodiments may implement anynumber of processing nodes. Similarly, as illustrated in FIG. 3, aprocessing node such as node 12 may include any number of processorcores, in various embodiments. In addition, various embodiments of thecomputer system 10 may also include different numbers of HT interfacesper node 12, and differing numbers of peripheral devices 13 coupled tothe node, etc.

Referring to FIG. 3, a block diagram of another embodiment of a computersystem 10 is shown. Components that correspond to those shown in FIG. 1are numbered identically for clarity and simplicity. Similar to thecomputer system 10 of FIG. 1, computer system 10 of FIG. 3 includes aprocessing node 312 coupled to a memory 14 and to peripheral devices 13Aand 13B. However, processing node 312 of FIG. 3 is shown with multipleprocessor cores, labeled processor core 15A, processor core 15B andprocessor core 15 n, where n is used to denote that there may be anynumber of processor cores.

In the embodiment illustrated in FIG. 3, interconnect 60 may performfunctions similar to the functions of interconnect 50 described inconjunction with the descriptions of FIG. 1 and FIG. 2. Specifically,interconnect 60 may be configurable to operate in various modes. Whenoperating in a first mode such as a test mode, for example, interconnect60 may be configured via a configuration input port 55 to interchangethe connections between each of processor core 15A, processor core 15B,processor core 15 n and node controller 20 such that transactionsoriginating at one processor core (e.g., 15A) are made to look as ifthey originated at the other processor core (e.g., 15 n). However, sincethere are additional processor cores 15, there may be additional similarcircuitry (not shown) included within interconnect 60. For example, inone embodiment, additional buffers (e.g., 210, 220) may be employed.

Although the embodiments above have been described in considerabledetail, numerous variations and modifications will become apparent tothose skilled in the art once the above disclosure is fully appreciated.It is intended that the following claims be interpreted to embrace allsuch variations and modifications.

1. A processing node comprising: a plurality of processor cores, eachconfigured to execute program instructions; a controller configured toschedule transactions received from each processor core of the pluralityof processor cores; and an interconnect coupled to convey between afirst processor core of the plurality of processor cores and thecontroller, transactions that each include a first correspondingindicator that indicates the source of the transaction and to conveytransactions between a second processor core of the plurality ofprocessor cores and the controller, transactions that each include asecond corresponding indicator that indicates the source of thetransaction; wherein when operating in a first mode, the interconnect isconfigurable to cause the first indicator to indicate that thecorresponding transactions were conveyed from the second processor coreand to cause the second indicator to indicate that the correspondingtransactions were conveyed from the first processor core.
 2. Theprocessing node as recited in claim 1, wherein when operating in thefirst mode, the interconnect is further configurable to causetransactions, sent from the controller, having the first processor coreas a destination to be routed to the second processor core and to causetransactions, sent from the controller, having the second processor coreas a destination to be routed to the first processor core.
 3. Theprocessing node as recited in claim 1, wherein when operating in asecond mode, the interconnect is further configurable to cause the firstindicator to indicate that the corresponding transactions were conveyedfrom the first processor core and to cause the second indicator toindicate that the corresponding transactions were conveyed from thesecond processor core.
 4. The processing node as recited in claim 1,wherein the interconnect includes a storage for storing a value thatindicates whether to operate the interconnect in one of the first modeand the second mode.
 5. The processing node as recited in claim 4,wherein in response to detecting a predetermined value in the storage,the interconnect is configured to operate in the first mode.
 6. Theprocessing node as recited in claim 4, wherein the processing nodefurther includes a configuration input port used for accessing thestorage and for storing the predetermined value therein.
 7. Theprocessing node as recited in claim 6, wherein the configuration inputis a five-pin serial boundary scan test port that includes TRST, TCK,TMS, TDI, and TDO signals.
 8. The processing node as recited in claim 1,wherein the first mode is a test mode and the transactions areresponsive to a test vector stimulus.
 9. The processing node as recitedin claim 1, wherein the interconnect is configured to convey eachtransaction on a respective packet interconnect.
 10. The processing nodeas recited in claim 1, wherein the indicator includes one or more bitsof a source field of a packet in each transaction.
 11. A methodcomprising: providing a plurality of processor cores on an integratedcircuit; providing a controller configured to schedule transactionsreceived from each processor core of the plurality of processor cores;conveying transactions between a first processor core of the pluralityof processor cores and the controller transactions that each include afirst corresponding indicator that indicates the source of thetransaction; and conveying transactions between a second processor coreof the plurality of processor cores and the controller transactions thateach include a second corresponding indicator that indicates the sourceof the transaction; wherein when operating in a first mode, causing thefirst indicator to indicate that the corresponding transactions wereconveyed from the second processor core and causing the second indicatorto indicate that the corresponding transactions were conveyed from thefirst processor core.
 12. The method as recited in claim 11, furthercomprising when operating in the first mode, causing transactions, sentfrom the controller and having the first processor core as adestination, to be routed to the second processor core and to causetransactions, sent from the controller and having the second processorcore as a destination to be routed to the first processor core.
 13. Themethod as recited in claim 11, further comprising when operating in asecond mode, causing the first indicator to indicate that thecorresponding transactions were conveyed from the first processor coreand causing the second indicator to indicate that the correspondingtransactions were conveyed from the second processor core.
 14. Themethod as recited in claim 11, further comprising storing a value thatindicates whether to operate the interconnect in one of the first modeand the second mode.
 15. The method as recited in claim 14, furthercomprising operating in the first mode in response to detecting apredetermined value in the storage.
 16. The method as recited in claim14, further comprising accessing the storage and storing thepredetermined value therein via a configuration input port.
 17. Themethod as recited in claim 16, wherein the configuration input is afive-pin serial boundary scan test port that includes TRST, TCK, TMS,TDI, and TDO signals.
 18. The method as recited in claim 11, furthercomprising conveying each transaction on a respective packetinterconnect.
 19. The method as recited in claim 11, wherein theindicator includes one or more bits of a source field of a packet ineach transaction.
 20. A computer system comprising: a memory; and aprocessing node coupled to the memory, wherein the processing nodeincludes: a plurality of processor cores, each configured to executeprogram instructions; a controller configured to schedule transactionsreceived from each processor core of the plurality of processor cores;and an interconnect coupled to convey between a first processor core ofthe plurality of processor cores and the controller, transactions thateach include a first corresponding indicator that indicates the sourceof the transaction and to convey transactions between a second processorcore of the plurality of processor cores and the controller,transactions that each include a second corresponding indicator thatindicates the source of the transaction; wherein when operating in afirst mode, the interconnect is configurable to cause the firstindicator to indicate that the corresponding transactions were conveyedfrom the second processor core and to cause the second indicator toindicate that the corresponding transactions were conveyed from thefirst processor core.
 21. A processing node comprising: a plurality ofprocessor cores, each configured to execute program instructions; acontroller configured to schedule transactions received from eachprocessor core of the plurality of processor cores; and an interconnectcoupled to convey between each processor core of the plurality ofprocessor cores and the controller, transactions that each include acorresponding indicator that indicates the source of the transaction;wherein when operating in a first mode, the interconnect is configurableto cause the indicator to indicate that the corresponding transactionwas conveyed from a different processor core of the plurality ofprocessor cores than the processor core that is the source of thetransaction.